This invention relates to computer-graphics systems, and more particularly to frame buffers split among multiple blocks in memory.
An interesting variety of small consumer devices are appearing. Portable computing and/or communication devices such as the personal digital assistant (PDA), Pocket PC, and smart cellular phones have an astonishing computing power for such small devices. These portable, often hand-held, computing devices often use a very-large-scale-integration (VLSI) chip that includes a microprocessor or central processing unit (CPU), memory, and I/O controllers on a single silicon chip known as a System-On-a-Chip (SOC).
These consumer devices run on battery power to achieve portability. The battery must be made small and light to keep the size and weight of the overall device small. Such small batteries necessitate the use of low-power chips including the SOC.
The SOC can include an on-chip static random-access memory (SRAM). Program running on the SOC's CPU can access data from an on-chip read-only-memory (ROM) and write data to the on-chip SRAM. Using the on-chip SRAM reduces power, since this avoids access cycles to an external dynamic-random-access memory (DRAM) that require more power to drive the larger off-chip capacitances.
Some accesses of the external DRAM may still be needed to load a very large program into the SRAM, or to fetch very large data files. Once these are stored and fetched, the external DRAM can be powered down while the program and frame buffer are located and executed within the on-chip SRAM. Use of the on-chip SRAM also improves performance, as SRAM access times are faster than access times to the external DRAM.
The SOC may include a graphics controller that continuously reads pixel data from a frame buffer and sends these pixels off-chip from the SOC to a display. The display can be a small liquid crystal display (LCD) that requires little power, or other compact display. The frame buffer can be a portion of the on-chip SRAM that is written by the CPU when updating the display. Using the internal SRAM for the frame buffer can further save power, since external accesses of an external frame-buffer memory are avoided.
However, larger, more colorful displays running at higher-resolution modes may require a large frame buffer to store a large number of pixels. Higher-color modes require more storage bits per pixel, and higher resolutions have more pixels to store. The on-chip SRAM may need to be enlarged to provide sufficient capacity for these larger frame buffers. However, larger on-chip SRAMs increase the SOC die size and reduce manufacturing yield. The SOC may even become too expensive for many low-cost consumer devices.
For example, a display of 320×240 pixels having one byte per pixel requires 76,000 bytes, which fits in a 100 Kilo-Byte (KB) SRAM. However, a more colorful display using 16 bits per pixel requires about 150 KB, which is larger than the 100 KB SRAM.
The frame buffer could be split among the on-chip SRAM and the external DRAM. However, all software programs running on the CPU expect the frame buffer to be a single, continuous block of address. Re-writing the many programs that can run on the CPU to allow for a split frame buffer is not practical. Programs are written expecting a conventional frame buffer with a contiguous block of addresses.
What is desired is a SOC that supports a frame buffer that can be split among multiple blocks of memory in the internal SRAM and the external DRAM. A graphics controller that can re-assemble pixels from the multiple blocks is desirable. A SOC that has a high-power display mode that splits the frame buffer between the on-chip SRAM and the external DRAM, and with a low-power display mode that only uses the on-chip SRAM is desired. It is further desired that the frame buffer appear to be a single, contiguous block of memory to programs executing on the CPU.